The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 25, 2025
Filed:
Nov. 18, 2021
Applicant:
Bar Ilan University, Ramat Gan, IL;
Inventors:
Joseph Shor, Tel Mond, IL;
Yitzhak Schifmann, Bet Horon, IL;
Inbal Stanger, Modiin, IL;
Netanel Shavit, Ramla, IL;
Edison Ramiro Taco Lasso, Quito, EC;
Alexander Fish, Tel Mond, IL;
Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/30 (2006.01); G01R 19/165 (2006.01); H03K 19/003 (2006.01);
U.S. Cl.
CPC ...
H03K 19/003 (2013.01); G01R 19/16538 (2013.01); G06F 1/30 (2013.01);
Abstract
A technique to mitigate timing errors induced by power supply droops includes an inverter-based droop detector as well as Dual Mode Logic (DML) to achieve a droop-resist ant timing response. The droop detector is based on capacitor ratios and is thus less sensitive to Process/Voltage/Temperature (PVT) and to random offset than the prior art. The DML can alter its power/performance ratio based on the droop level input it receives from the detector, such that the critical timings are preserved.