The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 2025

Filed:

Oct. 19, 2022
Applicant:

Murata Manufacturing Co., Ltd., Kyoto, JP;

Inventor:

Gary Chunshien Wu, San Diego, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 1/08 (2006.01); H02M 1/088 (2006.01); H02M 7/5387 (2007.01);
U.S. Cl.
CPC ...
H02M 1/08 (2013.01); H02M 1/088 (2013.01); H02M 7/5387 (2013.01);
Abstract

Circuitry and methods for an improved gate driver circuit for power converters. The improved gate driver circuit substantially reduces propagation delay and transition losses in the floating-gate side of the gate driver circuit. One embodiment includes an inverter having an input configured to receive a state transition signal and an output configured to be coupled to a control input of a switching device. The inverter includes a first NFET having a control gate configured to be coupled to the state transition signal, a second NFET having a control gate coupled to the output of a reference circuit, and a PFET having a control gate configured to be coupled to the state transition signal, wherein the output of the inverter is a node between the conduction channels of the first NFET and the second NFET and the conduction channels of the first NFET, second NFET, and PFET are coupled in series.


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