The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 2025

Filed:

Mar. 15, 2024
Applicant:

Macom Technology Solutions Holdings, Inc., Lowell, MA (US);

Inventors:

Allen W. Hanson, Cary, NC (US);

Chuanxin Lian, Westford, MA (US);

Wayne Mack Struble, Franklin, MA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 21/76 (2006.01); H01L 21/765 (2006.01); H01L 29/06 (2006.01); H01L 29/20 (2006.01); H01L 29/778 (2006.01); H01L 29/872 (2006.01);
U.S. Cl.
CPC ...
H01L 29/402 (2013.01); H01L 21/7605 (2013.01); H01L 21/765 (2013.01); H01L 29/0692 (2013.01); H01L 29/2003 (2013.01); H01L 29/7786 (2013.01); H01L 29/872 (2013.01);
Abstract

Extrinsic structures formed outside the active regions of active devices can influence aging characteristics and performance of the active devices. An example integrated device including such an extrinsic structure includes an active region of a semiconductor device in a plurality of layers of semiconductor materials over a substrate, an isolation region in at least one of the layers of semiconductor materials, the isolation region extending around the semiconductor device in an area outside of the active region, an insulating layer over at least a portion of the active region and over at least a portion of the isolation region, a via in the isolation region and outside the active region, the via extending through the insulating layer and down to a conduction layer among the layers of semiconductor materials in the isolation region, and an interconnect within the via and directly on the conduction layer in the isolation region.


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