The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 2025

Filed:

Jan. 08, 2024
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Jun Hyuk Seo, Gyeonggi-do, KR;

Myoung Sik Chang, Gyeonggi-do, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); G06F 11/34 (2006.01); G06N 20/00 (2019.01); G06V 10/774 (2022.01); G06V 10/778 (2022.01); H01L 49/02 (2006.01); H01L 21/02 (2006.01); H01L 21/3213 (2006.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H01L 28/75 (2013.01); G06F 11/3409 (2013.01); G06N 20/00 (2019.01); G06V 10/774 (2022.01); G06V 10/778 (2022.01); H01L 21/02175 (2013.01); H01L 21/0223 (2013.01); H01L 21/02244 (2013.01); H01L 21/32134 (2013.01); H10B 12/315 (2023.02);
Abstract

A method for fabricating a semiconductor device includes: forming a mold structure including a mold layer and a supporter layer over a semiconductor substrate; forming an opening penetrating the mold structure; forming a protective layer on a bottom surface and a sidewall of the opening; forming a lower electrode over the protective layer; selectively etching the supporter layer to form a supporter that supports the lower electrode; removing the mold layer to define a non-exposed portion and an exposed portion of an outer wall of the protective layer; and selectively trimming the exposed portion of the protective layer to form a protective layer pattern between the supporter and the lower electrode.


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