The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 2025

Filed:

Jun. 13, 2022
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Ishwar Agarwal, Redmond, WA (US);

Bharat Pillilli, El Dorado Hills, CA (US);

Vishal Soni, Redmond, WA (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 21/55 (2013.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 12/0891 (2016.01); G06F 21/54 (2013.01); G06F 21/79 (2013.01);
U.S. Cl.
CPC ...
G06F 21/556 (2013.01); G06F 9/30047 (2013.01); G06F 9/3858 (2023.08); G06F 21/54 (2013.01); G06F 21/552 (2013.01); G06F 21/79 (2013.01);
Abstract

Systems and methods related to flush plus reload cache side-channel attack mitigation are described. An example method for mitigating a side-channel timing attack in a system including a processor having at least one cache is described. The method includes receiving a first instruction, where the first instruction, when executed by the processor, is configured to flush at least one cache line from the at least one cache associated with the processor. The method further includes, prior to execution of the first instruction by the processor, automatically mapping the first instruction to a second instruction such that the at least one cache line is not flushed from the at least one cache even in response to receiving the first instruction.


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