The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 2025

Filed:

Apr. 27, 2021
Applicant:

Imagination Technologies Limited, Kings Langley, GB;

Inventors:

Dave Roberts, Saratoga, CA (US);

Mario Sopena Novales, Hertfordshire, GB;

John W. Howson, Hertfordshire, GB;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 9/455 (2018.01); G06F 12/1009 (2016.01); G06F 13/16 (2006.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1009 (2013.01); G06F 9/45558 (2013.01); G06F 13/16 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01); G06F 2009/45583 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/151 (2013.01); G06F 2212/152 (2013.01); G06F 2212/651 (2013.01); G06F 2212/657 (2013.01);
Abstract

A method of GPU virtualization comprises allocating each virtual machine (or operating system running on a VM) an identifier by the hypervisor and then this identifier is used to tag every transaction deriving from a GPU workload operating within a given VM context (i.e. every GPU transaction on the system bus which interconnects the CPU, GPU and other peripherals). Additionally, dedicated portions of a memory resource (which may be GPU registers or RAM) are provided for each VM and whilst each VM can only see their allocated portion of the memory, a microprocessor within the GPU can see all of the memory. Access control is achieved using root memory management units which are configured by the hypervisor and which map guest physical addresses to actual memory addresses based on the identifier associated with the transaction.


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