The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2025

Filed:

Sep. 12, 2022
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Kyohei Nabesaka, Yokkaichi, JP;

Teruo Okina, Yokkaichi, JP;

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/27 (2023.01); H10B 43/20 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H10B 43/20 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02);
Abstract

A memory die includes an alternating stack of insulating layers and electrically conductive layers, a semiconductor material layer located over the alternating stack, a dielectric spacer layer located over the semiconductor material layer, a memory opening vertically extending through the alternating stack, through the semiconductor material layer, and at least partly through the dielectric spacer layer, a memory opening fill structure located in the memory opening and including a dielectric core, a vertical semiconductor channel having a hollow portion which surrounds the dielectric core and a pillar portion which does not surround the dielectric core, and a memory film, and a source layer located over the dielectric spacer layer and contacting the pillar portion. In one embodiment, a tubular spacer laterally surrounds the pillar portion, is laterally spaced from the pillar portion by a cylindrical portion of the memory film, and contacts a cylindrical sidewall of the semiconductor material layer.


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