The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2025

Filed:

Nov. 09, 2022
Applicant:

Microchip Technology Incorporated, Chandler, AZ (US);

Inventors:

Dixon Chen, Guangdong, CN;

John Junling Zang, Guangdong, CN;

Yanzi Xu, Guangdong, CN;

Venkatraman Iyer, Austin, TX (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04W 74/08 (2024.01); H04L 7/02 (2006.01); H04L 47/62 (2022.01); H04L 69/32 (2022.01); H04L 69/324 (2022.01); H04W 74/0833 (2024.01);
U.S. Cl.
CPC ...
H04W 74/085 (2013.01); H04L 7/02 (2013.01); H04L 47/62 (2013.01); H04L 69/32 (2013.01); H04L 69/324 (2013.01);
Abstract

On or more examples relate, generally, to an apparatus that includes a reconciliation sublayer of a physical layer, a reduced media independent interface (RMII) of the physical layer, and a logic circuit. Such a logic circuit may operate to receive a changed carrier sense signal provided by the reconciliation sublayer, generate a further changed carrier sense signal at least partially responsive to a prediction that the changed carrier sense signal would cause unintended signaling at the RMII, and provide the further changed carrier sense signal to the RMII.


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