The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2025

Filed:

Mar. 15, 2022
Applicant:

Keysight Technologies, Inc., Santa Rosa, CA (US);

Inventors:

Jonathan Lee Harrod, Austin, TX (US);

Shardendu Pandey, Cedar Park, TX (US);

Jonathan Glenn Stroud, Austin, TX (US);

Stefan Jan Johansson, Round Rock, TX (US);

Assignee:

KEYSIGHT TECHNOLOGIES, INC., Santa Rosa, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04L 43/062 (2022.01); H04L 43/00 (2022.01); H04L 43/028 (2022.01);
U.S. Cl.
CPC ...
H04L 43/062 (2013.01); H04L 43/028 (2013.01); H04L 43/14 (2013.01);
Abstract

A method for selectively processing a packet flow using a flow inspection engine is disclosed. The method includes receiving, by at least one hardware data plane processor component in a network packet broker, a plurality of packets associated with a packet flow, and forwarding, by the at least one hardware data plane processor component to at least one flow inspection engine, a copy of at least a portion of one or more of the initial packets of the packet flow. The method further includes providing, by the at least one hardware data plane processor component to the at least one flow inspection engine, packet flow statistical data resulting from a high throughput processing of the plurality of packets by the at least one hardware data plane processor component and generating, by the at least one flow inspection engine, metadata records using the copy at least a portion of the of the one or more of the initial packets and the packet flow statistical data, wherein the at least one hardware data plane processor component generates the statistical data from the plurality of packets independent of any instruction from the at least one flow inspection engine.


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