The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2025

Filed:

Jul. 24, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Daeyeol Yang, Suwon-si, KR;

Bohwan Jun, Suwon-si, KR;

Hongrak Son, Suwon-si, KR;

Geunyeong Yu, Suwon-si, KR;

Youngjun Hwang, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/11 (2006.01); H03M 13/00 (2006.01); H03M 13/13 (2006.01); H03M 13/15 (2006.01); H03M 13/19 (2006.01);
U.S. Cl.
CPC ...
H03M 13/116 (2013.01); H03M 13/1102 (2013.01); H03M 13/1108 (2013.01); H03M 13/1111 (2013.01); H03M 13/1137 (2013.01); H03M 13/1174 (2013.01); H03M 13/1177 (2013.01); H03M 13/611 (2013.01); H03M 13/616 (2013.01); H03M 13/6561 (2013.01); H03M 13/6563 (2013.01); H03M 13/13 (2013.01); H03M 13/152 (2013.01); H03M 13/19 (2013.01);
Abstract

A generalized low-density parity-check (G-LDPC) encoder, including a plurality of generalized constraint (GC) encoders configured to perform a plurality of GC encoding operations in parallel based on a GC code having a quasi-cyclic (QC) structure including information variable nodes, inner parity variable nodes, and super check nodes configured to perform multiple condition checks, wherein each GC encoder of the plurality of GC encoders includes a plurality of first logic circuits configured to perform a GC encoding operation of the plurality of GC encoding operations; and an LDPC encoder configured to perform an LDPC encoding operation based on an LDPC code having the QC structure, wherein the LDPC encoder includes a plurality of single check nodes configured to perform a single parity check, wherein the each GC encoder is configured to receive information bits, and to determine parity bits of a portion of inner parity bits corresponding to the information bits by enabling only a portion of the plurality of first logic circuits to perform the GC encoding operation, and wherein the LDPC encoder is configured to: obtain the inner parity bits by combining the parity bits obtained from the plurality of GC encoders, determine outer parity bits corresponding to the information bits and the inner parity bits by performing the LDPC encoding operation, and output the information bits, the inner parity bits, and the outer parity bits as a codeword.


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