The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2025

Filed:

Sep. 12, 2022
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Mai Araki, Kawasaki Kanagawa, JP;

Fumihiko Tachibana, Yokohama Kanagawa, JP;

Assignee:

KIOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/10 (2006.01); H03M 1/06 (2006.01); H03M 1/08 (2006.01); H03M 1/12 (2006.01); H03M 1/18 (2006.01); H04L 7/00 (2006.01); H04L 7/033 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1028 (2013.01); H03M 1/0609 (2013.01); H03M 1/0624 (2013.01); H03M 1/0836 (2013.01); H03M 1/181 (2013.01); H03M 1/1215 (2013.01); H04L 7/0025 (2013.01); H04L 7/0062 (2013.01); H04L 7/033 (2013.01);
Abstract

According to one embodiment, a semiconductor integrated circuit includes a first converter, a second converter, and an adjustment circuit. The first converter is configured to sample an analog signal and convert the sampled analog signal to a first digital value based on a first clock signal. The second converter is configured to sample the analog signal and convert the sampled analog signal to a second digital value based on a second clock signal shifted a first phase from the first clock signal. The adjustment circuit is configured to adjust at least one of a gain of each of the first digital value and the second digital value and a phase of each of the first clock signal and the second clock signal based on the first digital value and the second digital value.


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