The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 18, 2025
Filed:
Dec. 12, 2023
Qualcomm Incorporated, San Diego, CA (US);
Julian Puscar, Holly Springs, NC (US);
Burcin Serter Ergun, Poway, CA (US);
Brett Patrick Delaney, San Diego, CA (US);
Zhiqin Chen, San Diego, CA (US);
QUALCOMM INCORPORATED, San Diego, CA (US);
Abstract
A method for calibrating a phase locked loop (PLL) includes counting cycles of an output clock signal generated by the PLL until early phase lock signal is asserted when the cycles of the output clock signal counted within a first duration of time differ from a first target value by no more than a first maximum difference, counting cycles of the output clock signal until final phase lock signal is asserted when the cycles of the output clock signal counted within a second duration of time differ from a second target value by no more than a second maximum difference, the second duration of time being greater than the first duration of time, and using the output clock signal to control an operation in a physical layer circuit of a communication interface after the early phase lock signal is asserted and before the final phase lock signal is asserted.