The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 18, 2025
Filed:
Jun. 17, 2021
Intel Corporation, Santa Clara, CA (US);
Archanna Srinivasan, San Jose, CA (US);
Ravi Gutala, San Jose, CA (US);
Scott Weber, Piedmont, CA (US);
Aravind Dasu, Milpitas, CA (US);
Mahesh Iyer, Fremont, CA (US);
Eriko Nurvitadhi, Beaverton, OR (US);
Altera Corporation, San Jose, CA (US);
Abstract
A circuit system includes a first integrated circuit die having a first group of circuits configured to perform a first set of operations. The circuit system also includes a second integrated circuit die having a second group of circuits configured to start performing a second set of operations with a delay after the first group of circuits starts performing the first set of operations to reduce power supply voltage droop. The operations performed by the first and second groups of circuits can be interleaved with a fixed or a variable delay. Logic circuits can be partitioned into the first and the second groups of circuits based on predicted switching activity of the logic circuits. Decoupling capacitors in integrated circuit dies can be coupled together to reduce droop in a supply voltage during a high current event.