The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2025

Filed:

Nov. 28, 2022
Applicant:

Icometrue Company Ltd., Zhubei, TW;

Inventors:

Jin-Yuan Lee, Hsinchu, TW;

Mou-Shiung Lin, Hsinchu, TW;

Assignee:

iCometrue Company Ltd., Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2023.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H03K 19/17736 (2020.01); H03K 19/17796 (2020.01); H01L 23/14 (2006.01); H01L 23/532 (2006.01); H01L 27/118 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 21/563 (2013.01); H01L 23/3128 (2013.01); H01L 23/49827 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 24/17 (2013.01); H03K 19/17736 (2013.01); H03K 19/17796 (2013.01); H01L 21/561 (2013.01); H01L 23/145 (2013.01); H01L 23/147 (2013.01); H01L 23/53238 (2013.01); H01L 27/11803 (2013.01); H01L 27/11807 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01);
Abstract

A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.


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