The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 18, 2025
Filed:
May. 16, 2019
Genesys Logic, Inc., New Taipei, CN;
Woon-Sik Suh, New Taipei, CN;
GENESYS LOGIC, INC., NEW TAIPEI CITY, TAIWAN,, CN;
Abstract
An apparatus and a method of implementing activation logic for a neural network are described. The apparatus comprises an input unit, a first address translated look-up table, an intermediate storage unit, a second address translated look-up table, and an output unit. The first address translated look-up table includes (2{circumflex over ( )}n1) first entries that map to (2{circumflex over ( )}n1) addresses based on the n bits of the input unit. Each the (2{circumflex over ( )}n1) first entries includes (n1−1) first preset values. The intermediate storage unit includes (n−1) bits. The second address translated look-up table includes (2{circumflex over ( )}(n−1)) second entries that map to the (2{circumflex over ( )}(n−1)) bit addresses based on of the (n−1) bits of the intermediate storage unit. Each the (2{circumflex over ( )}(n−1)) second entries includes (n2+1) second preset values. The output unit is used for outputting n output data values by combining the (n1−1) first preset values and the (n2+1) second preset values.