The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2025

Filed:

Jan. 16, 2024
Applicant:

Lapis Technology Co., Ltd., Yokohama, JP;

Inventor:

Mitsuru Arai, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/147 (2006.01); G09G 3/20 (2006.01); G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
G06F 3/147 (2013.01); G09G 3/2096 (2013.01); G09G 3/3688 (2013.01); G09G 2310/0272 (2013.01); G09G 2310/0291 (2013.01); G09G 2310/066 (2013.01); G09G 2310/08 (2013.01); G09G 2370/14 (2013.01);
Abstract

An output driver according to the disclosure includes a differential signaling circuit that includes a first transistor that generates a bias current, first and second nodes, and a resistor circuit connected between the first and second nodes, and outputs voltages respectively at the first and second nodes as a pair of differential signals by supplying the bias current to one of the first and second nodes based on a level of the input signals, a differential voltage circuit that supplies a differential voltage representing a difference between a center voltage of voltages between the first node and the second node and a predetermined reference voltage to a gate of the first transistor; and a pre-emphasis circuit that executes a pre-emphasis processing in response to changes in the level of the input signal, generating a current based on the differential voltage and adding it to the bias current.


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