The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2025

Filed:

Jan. 03, 2023
Applicant:

Realtek Semiconductor Corporation, Hsinchu, TW;

Inventors:

Chao-Min Lai, Hsinchu, TW;

Chien-Liang Chen, Hsinchu, TW;

Ming-Tsung Tsai, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/30 (2006.01); G06F 1/10 (2006.01); G06F 9/4401 (2018.01); G06F 11/07 (2006.01);
U.S. Cl.
CPC ...
G06F 1/30 (2013.01); G06F 1/10 (2013.01); G06F 9/4401 (2013.01); G06F 9/442 (2013.01); G06F 11/0757 (2013.01); G06F 11/079 (2013.01);
Abstract

An electronic system includes a main chip, a non-volatile storage circuit, and a detector circuit. The main chip is configured to read first time of a clock circuit. The non-volatile storage circuit is coupled to the main chip. The main chip stores the first time into the non-volatile storage circuit. The detector circuit includes a first output terminal. The first output terminal is coupled to the main chip. When a cold boot event occurs, the main chip reads the first time from the non-volatile storage circuit, and determines a reason of the cold boot event according to the first time, a second time of the clock circuit, and a logic value at the first output terminal.


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