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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12250866 B1

PDFFull Text
Date of Patent:
Mar. 11, 2025

Filed:

Apr. 09, 2021

Display motherboard and method for manufacturing display substrate

Applicants:

Chengdu Boe Optoelectronics Technology Co., Ltd., Sichuan, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Yongjie Song, Beijing, CN;

Siyu Wang, Beijing, CN;

Shun Zhang, Beijing, CN;

Yi Zhang, Beijing, CN;

Fengli Ji, Beijing, CN;

Yuanqi Zhang, Beijing, CN;

Yi Qu, Beijing, CN;

Yan Huang, Beijing, CN;

Assignees:

CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan, CN;

BOE TECHNOLOGY GROUP CO., LTD., Beijing, CN;

Attorneys:

Nath, Goldberg & Meyer

Joshua B. Goldberg

Primary Examiner:

Ratisha Mehta

Assistant Examiner:

Brad A Knudson

Int. Cl.
CPC ...
H10K 59/88 (2023.01); H01L 27/12 (2006.01); H10K 59/12 (2023.01); H10K 59/121 (2023.01); H10K 59/122 (2023.01); H10K 59/131 (2023.01); H10K 59/80 (2023.01); H10K 71/00 (2023.01);
U.S. Cl.
CPC ...
H10K 59/88 (2023.02); H01L 27/124 (2013.01); H10K 59/1201 (2023.02); H10K 59/131 (2023.02); H10K 59/80515 (2023.02); H10K 59/1213 (2023.02); H10K 59/122 (2023.02); H10K 71/00 (2023.02);
Abstract

A display motherboard and a manufacturing method of a display substrate are provided. The display motherboard includes: a substrate including a valid area and an edge area, the valid area including a plurality of panel areas and a to-be-cut area, and the panel area including a display area and a frame area; multiple first power lines in each display area and the edge area and extending along a first direction; multiple first display electrodes in each display area and multiple virtual electrodes in the edge area, the first display electrodes and the virtual electrodes being in the same layer; wherein an orthographic projection of each first display electrode on the substrate overlaps an orthographic projection of at most one first power line on the substrate, and an orthographic projection of each virtual electrode on the substrate overlaps orthographic projections of at least two first power lines on the substrate.

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