The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 11, 2025
Filed:
May. 05, 2022
Applicant:
Richtek Technology Corporation, Zhubei, TW;
Inventors:
Kuo-Hsuan Lo, Taoyuan, TW;
Chien-Hao Huang, Penghu, TW;
Chu-Feng Chen, Hsibchu, TW;
Wu-Te Weng, Hsibchu, TW;
Assignee:
RICHTEK TECHNOLOGY CORPORATION, Zhubei, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/765 (2006.01); H10D 30/01 (2025.01); H10D 30/65 (2025.01); H10D 62/17 (2025.01); H10D 64/00 (2025.01); H10D 84/00 (2025.01);
U.S. Cl.
CPC ...
H10D 64/111 (2025.01); H01L 21/765 (2013.01); H10D 30/0281 (2025.01); H10D 30/65 (2025.01); H10D 62/393 (2025.01); H10D 84/151 (2025.01); H10D 30/0285 (2025.01);
Abstract
A power device includes: a semiconductor layer, a well region, a body region, a gate, a source, a drain, a first salicide block (SAB) layer and a second SAB layer. The first SAB layer is formed on a top surface of the semiconductor layer, and is located between the gate and the drain, wherein a part of the well is located vertically below and in contact with the first SAB layer. The second SAB layer is formed vertically above and in contact with the first SAB layer.