The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 11, 2025

Filed:

Jun. 06, 2022
Applicants:

Beijing Superstring Academy of Memory Technology, Beijing, CN;

Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;

Inventor:

Huilong Zhu, Poughkeepsie, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 21/28 (2025.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6728 (2025.01); H01L 21/28088 (2013.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6739 (2025.01); H10D 30/6757 (2025.01);
Abstract

A semiconductor device and a method of manufacturing the same, and an electronic apparatus including the semiconductor device are provided. The semiconductor device includes: an active region, on a substrate, extending substantially in a vertical direction; a gate stack formed around at least a part of a periphery of the active region, the active region including a channel region opposite to the gate stack, and a first source/drain region and a second source/drain region, and the gate stack including a gate dielectric layer, a work function tuning layer and a gate electrode material layer, and the work function tuning layer being between the gate electrode material layer and the channel region; and a first low-k dielectric layer extending from a first end of the work function tuning layer to surround a first corner of an end portion, on a side facing the channel region, of the gate electrode material layer.


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