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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12250814 B1

PDFFull Text
Date of Patent:
Mar. 11, 2025

Filed:

Jun. 13, 2022

Through-stack contact via structures for a three-dimensional memory device and methods of forming the same

Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Kenichi Shimomura, Yokkaichi, JP;

Takayuki Maekura, Yokkaichi, JP;

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:

THE MARBURY LAW GROUP PLLC

Primary Examiner:

Jaehwan Oh

Int. Cl.
CPC ...
H01L 23/522 (2006.01); G11C 16/04 (2006.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
H10B 41/35 (2023.02); G11C 16/0483 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02);
Abstract

A three-dimensional memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers, a second-tier alternating stack of second insulating layers and second electrically conductive layers, a vertically alternating sequence of insulating plates and dielectric material plates laterally surrounded by the second-tier alternating stack, memory openings vertically extending through each layer within the first-tier alternating stack and the second-tier alternating stack, memory opening fill structures located in the memory openings, first contact via structures vertically extending through the vertically alternating sequence and contacting a respective one of the first electrically conductive layers, and second contact via structures contacting a respective one of the second electrically conductive layers.

Find Patent Forward Citations

Shimomura, Kenichi. (2025). Through-stack contact via structures for a three-dimensional memory device and methods of forming the same (U.S. Patent No. 12250814). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12250814

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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