The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 11, 2025
Filed:
May. 15, 2023
Applicant:
Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;
Inventor:
Huilong Zhu, Poughkeepsie, NY (US);
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); B82Y 10/00 (2011.01); G05B 23/02 (2006.01); G06T 19/00 (2011.01); H01L 21/02 (2006.01); H01L 21/223 (2006.01); H01L 21/225 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01); H01L 21/324 (2006.01); H01L 21/822 (2006.01); H01L 21/8234 (2006.01); H01L 23/522 (2006.01); H01L 27/092 (2006.01); H01L 29/04 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/15 (2006.01); H01L 29/165 (2006.01); H01L 29/205 (2006.01); H01L 29/267 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/778 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H04N 7/18 (2006.01); H04N 23/698 (2023.01); G06F 3/04817 (2022.01); G06F 3/0482 (2013.01); G06V 20/40 (2022.01); H01L 21/3105 (2006.01); H04N 13/111 (2018.01); H04N 13/332 (2018.01); H04N 13/366 (2018.01); H04N 13/398 (2018.01); H04N 23/90 (2023.01);
U.S. Cl.
CPC ...
H01L 21/823885 (2013.01); B82Y 10/00 (2013.01); G05B 23/0216 (2013.01); G06T 19/006 (2013.01); H01L 21/02532 (2013.01); H01L 21/02636 (2013.01); H01L 21/2236 (2013.01); H01L 21/2252 (2013.01); H01L 21/2253 (2013.01); H01L 21/2258 (2013.01); H01L 21/3065 (2013.01); H01L 21/3083 (2013.01); H01L 21/324 (2013.01); H01L 21/8221 (2013.01); H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 21/82345 (2013.01); H01L 21/823475 (2013.01); H01L 21/823487 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823842 (2013.01); H01L 21/823864 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 23/5221 (2013.01); H01L 27/092 (2013.01); H01L 27/0925 (2013.01); H01L 29/04 (2013.01); H01L 29/0638 (2013.01); H01L 29/0653 (2013.01); H01L 29/0676 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/1054 (2013.01); H01L 29/1083 (2013.01); H01L 29/1095 (2013.01); H01L 29/152 (2013.01); H01L 29/165 (2013.01); H01L 29/205 (2013.01); H01L 29/267 (2013.01); H01L 29/41741 (2013.01); H01L 29/42376 (2013.01); H01L 29/42392 (2013.01); H01L 29/45 (2013.01); H01L 29/66431 (2013.01); H01L 29/66439 (2013.01); H01L 29/66462 (2013.01); H01L 29/66469 (2013.01); H01L 29/66522 (2013.01); H01L 29/66545 (2013.01); H01L 29/6656 (2013.01); H01L 29/66666 (2013.01); H01L 29/66712 (2013.01); H01L 29/66742 (2013.01); H01L 29/775 (2013.01); H01L 29/7788 (2013.01); H01L 29/7813 (2013.01); H01L 29/7827 (2013.01); H01L 29/7848 (2013.01); H01L 29/78618 (2013.01); H01L 29/78642 (2013.01); H01L 29/78696 (2013.01); H04N 7/181 (2013.01); H04N 23/698 (2023.01); G05B 2219/32014 (2013.01); G06F 3/04817 (2013.01); G06F 3/0482 (2013.01); G06V 20/40 (2022.01); G06V 20/44 (2022.01); G06V 2201/06 (2022.01); H01L 21/31053 (2013.01); H01L 21/823828 (2013.01); H01L 29/0649 (2013.01); H04N 13/111 (2018.05); H04N 13/332 (2018.05); H04N 13/366 (2018.05); H04N 13/398 (2018.05); H04N 23/90 (2023.01);
Abstract
There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate, and a first device and a second device formed on the substrate. Each of the first device and the second device includes a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and also a gate stack surrounding a periphery of the channel layer. The channel layer of the first device and the channel layer of the second device are substantially co-planar.