The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 11, 2025

Filed:

Mar. 10, 2022
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Prakash Bangalore Prabhakar, San Jose, CA (US);

Gentaro Hirota, San Jose, CA (US);

Ronny Krashinsky, Portola Valley, CA (US);

Ze Long, San Jose, CA (US);

Brian Pharris, Cary, NC (US);

Rajballav Dash, San Jose, CA (US);

Jeff Tuckey, Saratoga, CA (US);

Jerome F. Duluk, Jr., Palo Alto, CA (US);

Lacky Shah, Los Altos Hills, CA (US);

Luke Durant, San Jose, CA (US);

Jack Choquette, Palo Alto, CA (US);

Eric Werness, San Jose, CA (US);

Naman Govil, Sunnyvale, CA (US);

Manan Patel, San Jose, CA (US);

Shayani Deb, Seattle, WA (US);

Sandeep Navada, San Jose, CA (US);

John Edmondson, Arlington, MA (US);

Greg Palmer, Cedar Park, TX (US);

Wish Gandhi, Sunnyvale, CA (US);

Ravi Manyam, San Ramon, CA (US);

Apoorv Parle, San Jose, CA (US);

Olivier Giroux, Santa Clara, CA (US);

Shirish Gadre, Fremont, CA (US);

Steve Heinrich, Madison, AL (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/52 (2006.01); G06F 9/54 (2006.01); G06F 13/16 (2006.01); G06T 1/60 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3851 (2013.01); G06F 9/522 (2013.01); G06F 9/544 (2013.01); G06F 13/1663 (2013.01); G06T 1/60 (2013.01);
Abstract

Distributed shared memory (DSMEM) comprises blocks of memory that are distributed or scattered across a processor (such as a GPU). Threads executing on a processing core local to one memory block are able to access a memory block local to a different processing core. In one embodiment, shared access to these DSMEM allocations distributed across a collection of processing cores is implemented by communications between the processing cores. Such distributed shared memory provides very low latency memory access for processing cores located in proximity to the memory blocks, and also provides a way for more distant processing cores to also access the memory blocks in a manner and using interconnects that do not interfere with the processing cores' access to main or global memory such as hacked by an L2 cache. Such distributed shared memory supports cooperative parallelism and strong scaling across multiple processing cores by permitting data sharing and communications previously possible only within the same processing core.


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