The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 11, 2025

Filed:

May. 19, 2021
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Winnie W. Yeung, San Jose, CA (US);

Cheng Li, Sunnyvale, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/0811 (2016.01); G06F 12/02 (2006.01); G06F 12/0846 (2016.01); G06F 12/0891 (2016.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0811 (2013.01); G06F 12/0246 (2013.01); G06F 12/0846 (2013.01); G06F 12/0891 (2013.01); G06F 13/1605 (2013.01); G06F 13/1668 (2013.01);
Abstract

Techniques are disclosed relating to multi-block fetches for cache misses. In some embodiments, cache tag circuitry maintains a tag value that is shared by multiple cache blocks. In response to a miss, the cache may initiate a fetch request to a next level cache or memory. Aggregation circuitry may aggregate multiple fetch requests for cache blocks that share the tag value and fetch circuitry may initiate a single multi-block fetch operation to the next level cache or memory that returns cache blocks for the aggregated multiple fetch requests. In various embodiments, disclosed techniques may improve performance (e.g., by reducing fetch bus transactions), reduce power consumption, or both, relative to traditional techniques.


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