The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 11, 2025

Filed:

Mar. 07, 2023
Applicant:

Dell Products L.p., Round Rock, TX (US);

Inventors:

Michael Rijo, San Jose, CA (US);

Robert Proulx, Holden, MA (US);

Assignee:

Dell Products L.P., Round Rock, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/07 (2006.01); G06F 11/20 (2006.01); G11C 16/08 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G06F 11/2094 (2013.01); G06F 11/0793 (2013.01); G11C 16/08 (2013.01); G11C 16/3404 (2013.01);
Abstract

A data retention event preparation/recovery system includes a chassis, a plurality of NAND subsystems included in the chassis, and a data retention event preparation/recovery subsystem that is included in the chassis and coupled to the plurality of NAND subsystems. The data retention event preparation/recovery subsystem determines that the plurality of NAND subsystems will experience a data retention event and, in response, identifies a first subset of the plurality of NAND subsystems that exceed an error threshold, identifies at least one overprovisioned block in the plurality of NAND subsystem, copies data that is stored on the first subset of the plurality of NAND subsystems to the at least one overprovisioned block in the plurality of NAND subsystems, and power offs the plurality of NAND subsystems to begin the data retention event.


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