The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 04, 2025
Filed:
Jun. 29, 2021
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventors:
Kun Young Lee, Gyeonggi-do, KR;
Nam Kuk Kim, Gyeonggi-do, KR;
Assignee:
SK hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H01L 27/105 (2023.01); H10B 12/00 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/40 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10B 43/50 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H10B 12/03 (2023.02); H10B 12/30 (2023.02); H10B 12/50 (2023.02); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02);
Abstract
Embodiments of the present invention provide a hybrid memory and a hybrid memory manufacturing method including both a volatile memory and a nonvolatile memory on a single substrate so as to increase an operation speed of a semiconductor device and reduce manufacturing cost. A hybrid memory includes: a substrate; a non-volatile memory including an alternating stack in which a plurality of insulation layers and a plurality of horizontal word lines are alternately stacked on the substrate; and a volatile memory including a capacitor, the capacitor penetrating through the alternating stack.