The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 04, 2025

Filed:

May. 13, 2022
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Christian Cornelius Russ, Diedorf, DE;

Kai Esmark, Neuried, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 9/04 (2006.01); H01L 25/065 (2023.01); H01L 27/02 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
H02H 9/046 (2013.01); H01L 25/0655 (2013.01); H01L 27/0255 (2013.01); H01L 27/0266 (2013.01); H01L 27/0288 (2013.01); H01L 27/0292 (2013.01); H01L 23/538 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 25/18 (2013.01); H01L 27/0296 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/48175 (2013.01); H01L 2224/49175 (2013.01);
Abstract

The described techniques address issues associated with electrostatic discharge (ESD) protection for multi-die integrated circuits (ICs). The techniques include the use of two or more semiconductor dies within a multi-die IC, which may include a first semiconductor die without ESD protection but with full ESD exposure. The first semiconductor receives ESD protection via a second semiconductor die that is integrated as part of the same package with the first semiconductor die. The second semiconductor die may be electrically more remote from ESD-exposed pins compared to the first semiconductor die. The first semiconductor die may include integrated passive devices. The second semiconductor die enables ESD protection for both semiconductor dies in the same integrated IC package.


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