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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12243840 B1

PDFFull Text
Date of Patent:
Mar. 04, 2025

Filed:

Jul. 24, 2020

Wirebondable interposer for flip chip packaged integrated circuit die

Applicant:

Samtec, Inc., New Albany, IN (US);

Inventors:

Edwin Loy, Fremont, CA (US);

Yan Yang Zhao, Fremont, CA (US);

Chihhao Chen, Fremont, CA (US);

Assignee:

SAMTEC, INC., New Albany, IN (US);

Attorney:

BakerHostetler

Primary Examiner:

Nicholas J Tobergte

Assistant Examiner:

William Henry Anderson

Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 21/50 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H04B 10/80 (2013.01); H04B 10/40 (2013.01);
U.S. Cl.
CPC ...
H01L 24/14 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/50 (2013.01); H01L 23/49811 (2013.01); H01L 23/49822 (2013.01); H01L 23/4985 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 23/5387 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 24/05 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05076 (2013.01); H01L 2224/05078 (2013.01); H01L 2224/05082 (2013.01); H01L 2224/05557 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81815 (2013.01); H04B 10/40 (2013.01); H04B 10/808 (2013.01);
Abstract

A variety of methods and arrangements to convert a flip chip IC die package into a wirebondable component using an interposer are described. The interposer has an insulating layer and a patterned metal layer attached to one side of the insulating layer. The patterned metal layer is electrically connected to the IC die using solder bumps. The interposer has wirebond pads on a side of the interposer opposed to the side of the interposer having the electrical connection between the IC die and solder bumps. The interposer may be a thin organic laminate or a flexible printed circuit board.

Find Patent Forward Citations

Loy, Edwin. (2025). Wirebondable interposer for flip chip packaged integrated circuit die (U.S. Patent No. 12243840). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12243840

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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