The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 04, 2025

Filed:

Dec. 16, 2021
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventor:

Jin Ha Kim, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 23/535 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); H01L 23/53266 (2013.01); H01L 23/535 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02);
Abstract

A memory device, and a method of manufacturing the same, includes interlayer insulation layers spaced apart from each other and stacked, gate lines formed between the interlayer insulation layers, and a plug vertically passing through the interlayer insulation layers and the gate lines. Each of the gate lines includes a barrier layer formed along an inner wall of the interlayer insulation layer and the plug, a first conductive layer surrounded by the barrier layer, and a second conductive layer surrounded by the first conductive layer. A material of the second conductive layer is different from a material of the first conductive layer, and a size of the second conductive layer is variable along a direction in which the gate lines extend.


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