The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 04, 2025

Filed:

Feb. 14, 2024
Applicant:

Nichia Corporation, Anan, JP;

Inventors:

Tadaaki Miyata, Yokohama, JP;

Yoshihiro Kimura, Yokohama, JP;

Masatoshi Nakagaki, Komatsushima, JP;

Assignee:

NICHIA CORPORATION, Anan, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 23/373 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/367 (2013.01); H01L 23/3736 (2013.01); H01L 23/49811 (2013.01); H01L 23/49838 (2013.01);
Abstract

A method for manufacturing a semiconductor device include: providing a submount that has a first surface, a second surface located on a side opposite the first surface, and at least one lateral surface located between the first surface and the second surface, the submount including: a groove located at the second surface, a heat dissipation portion located at the second surface, at least one end face through channel located at the at least one lateral surface, and an electrode pattern on the first surface; physically joining the heat dissipation portion to a package substrate by a first joint material; and after the step of physically joining the heat dissipation portion to the package substrate, disposing a second joint material inside the at least one end face through channel to electrically connect the electrode pattern and the package substrate.


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