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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12243739 B1

PDFFull Text
Date of Patent:
Mar. 04, 2025

Filed:

Oct. 23, 2019

Semiconductor wafer and method for manufacturing same

Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventors:

Yuki Taketomi, Tokyo, JP;

Kohei Miki, Tokyo, JP;

Shinichi Miyakuni, Tokyo, JP;

Assignee:

Mitsubishi Electric Corporation, Tokyo, JP;

Attorney:

Studebaker Brackett PLLC

Primary Examiner:

Maria V Ewald

Assistant Examiner:

Donald M Flores, Jr

Int. Cl.
CPC ...
C30B 29/40 (2006.01); C23C 16/04 (2006.01); C23C 16/30 (2006.01); C23C 16/34 (2006.01); C23C 16/50 (2006.01); C30B 23/04 (2006.01); C30B 25/04 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02002 (2013.01); C23C 16/042 (2013.01); C23C 16/303 (2013.01); C23C 16/345 (2013.01); C23C 16/50 (2013.01); C30B 23/04 (2013.01); C30B 25/04 (2013.01); C30B 29/406 (2013.01); H01L 21/02381 (2013.01); H01L 21/02433 (2013.01); H01L 21/0254 (2013.01); H01L 21/02639 (2013.01); H01L 21/02664 (2013.01);
Abstract

A method for manufacturing a semiconductor wafer according to the invention of the present application includes a first step of forming a gallium nitride growth layer which is divided into a plurality of small sections, on an upper surface of a silicon substrate and a second step of filling portions between the plurality of small sections with an insulating film, wherein the insulating film exerts stress to the silicon substrate in a direction opposite to a direction in which the gallium nitride growth layer exerts stress on the silicon substrate.

Find Patent Forward Citations

Taketomi, Yuki. (2025). Semiconductor wafer and method for manufacturing same (U.S. Patent No. 12243739). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12243739

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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