The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 04, 2025
Filed:
Dec. 21, 2023
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventors:
Devanathan Varadarajan, Allen, TX (US);
Lei Wu, Sugar Land, TX (US);
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/12 (2006.01); G01R 31/3185 (2006.01); G11C 29/02 (2006.01); G11C 29/10 (2006.01); G11C 29/14 (2006.01); G11C 29/16 (2006.01); G11C 29/26 (2006.01); G11C 29/32 (2006.01); G11C 29/36 (2006.01);
U.S. Cl.
CPC ...
G11C 29/12015 (2013.01); G01R 31/318594 (2013.01); G01R 31/318597 (2013.01); G11C 29/022 (2013.01); G11C 29/023 (2013.01); G11C 29/10 (2013.01); G11C 29/1201 (2013.01); G11C 29/14 (2013.01); G11C 29/16 (2013.01); G11C 29/26 (2013.01); G11C 29/32 (2013.01); G11C 29/36 (2013.01);
Abstract
Methods to test functional memory interface logic of a core under test utilize a built-in-self-test (BIST) controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at BIST mode, an at-speed functional mode is utilized to capture a desired memory output.