The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 04, 2025

Filed:

Nov. 21, 2023
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Sukalpa Biswas, Fremont, CA (US);

Farid Nemati, Redwood City, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/402 (2006.01); G11C 5/02 (2006.01); G11C 5/04 (2006.01); G11C 5/06 (2006.01); G11C 7/02 (2006.01); G11C 11/406 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 25/10 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4023 (2013.01); G11C 5/025 (2013.01); G11C 5/04 (2013.01); G11C 5/06 (2013.01); G11C 5/063 (2013.01); G11C 7/02 (2013.01); G11C 11/40607 (2013.01); H01L 24/00 (2013.01); H01L 25/0652 (2013.01); H01L 25/105 (2013.01); H01L 25/0657 (2013.01); H01L 27/0203 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/15311 (2013.01);
Abstract

In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g., an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.


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