The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 04, 2025

Filed:

Oct. 19, 2023
Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Dong Woo Kim, Yongin-si, KR;

Kwi Hyun Kim, Yongin-si, KR;

Yeon Kyung Kim, Yongin-si, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3258 (2016.01); G09G 3/32 (2016.01); G09G 3/3208 (2016.01); G09G 3/3233 (2016.01); G09G 3/3266 (2016.01); G09G 3/3275 (2016.01);
U.S. Cl.
CPC ...
G09G 3/3258 (2013.01); G09G 3/3233 (2013.01); G09G 3/3266 (2013.01); G09G 3/3275 (2013.01); G09G 3/32 (2013.01); G09G 3/3208 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/043 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0243 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0646 (2013.01); G09G 2330/021 (2013.01);
Abstract

A pixel includes a light emitting element, a first transistor including an electrode connected to a first power source line via a first node, another electrode connected to a second power source line via a second node and the light emitting element, and another electrode connected to a third node. The pixel further includes a second transistor connected between a data line and the second node and having a gate electrode connected to a scan line, a third transistor connected between the first node and the third node and having a gate electrode connected to the scan line, a fourth transistor connected between the first power source line and the first node and having a gate electrode connected to an emission control line, a first capacitor connected between the second node and the third node, and a second capacitor connected between a third power source line and the third node.


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