The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 04, 2025

Filed:

Apr. 06, 2023
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken, JP;

Inventors:

Shunpei Yamazaki, Tokyo, JP;

Yukinori Shima, Gunma, JP;

Masami Jintyou, Tochigi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09F 9/30 (2006.01); H01L 29/786 (2006.01); H10K 50/00 (2023.01); H10K 59/00 (2023.01);
U.S. Cl.
CPC ...
G09F 9/30 (2013.01); H10K 50/00 (2023.02); H01L 29/7869 (2013.01); H10K 59/00 (2023.02);
Abstract

A semiconductor device that can be highly integrated is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, a second insulating layer, a third insulating layer, and a first conductive layer. The third insulating layer is positioned over the semiconductor layer and includes a first opening over the semiconductor layer. The first conductive layer is positioned over the semiconductor layer, the first insulating layer is positioned between the first conductive layer and the semiconductor layer, and the second insulating layer is provided in a position that is in contact with a side surface of the first opening, the semiconductor layer, and the first insulating layer. The semiconductor layer includes a first portion overlapping with the first insulating layer, a pair of second portions between which the first portion is sandwiched and which overlap with the second insulating layer, and a pair of third portions between which the first portion and the pair of second portions are sandwiched and which overlap with neither the first insulating layer nor the second insulating layer. The first portion has a smaller width than the first opening and has a thinner shape of the semiconductor layer than the second portions, and the second portions have a thinner shape of the semiconductor layer than the third portions.


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