The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 04, 2025

Filed:

Mar. 29, 2021
Applicant:

Infineon Technologies Llc, San Jose, CA (US);

Inventors:

Prashant Kumar Saxena, Fremont, CA (US);

Vineet Agrawal, San Jose, CA (US);

Venkatraman Prabhakar, Pleasanton, CA (US);

Assignee:

Infineon Technologies LLC, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/08 (2023.01); G06F 7/544 (2006.01); G06N 3/063 (2023.01); G11C 16/04 (2006.01); G11C 16/24 (2006.01); H03M 1/12 (2006.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06F 7/5443 (2013.01); G06N 3/08 (2013.01); G11C 16/0466 (2013.01); G11C 16/24 (2013.01); H03M 1/12 (2013.01);
Abstract

A method can include, for each row of a nonvolatile memory (NVM) cell array, generating a multiply-accumulate (MAC) result for the row by applying input values on bit lines. Each MAC result comprising a summation of an analog current or voltage that is a function of each input value modified by a corresponding weight value stored by the NVM cells of the row. By operation of at least one multiplexer, one of the rows can be connected to an analog-to-digital converter (ADC) circuit to convert the analog current or voltage of the row into a digital MAC value. A storage element of each NVM cell can be configured to store a weight value that can vary between no less than three different values. Corresponding devices and systems are also disclosed.


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