The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 04, 2025

Filed:

Mar. 14, 2023
Applicant:

Sambanova Systems, Inc., Palo Alto, CA (US);

Inventors:

Conrad Alexander Turlik, Palo Alto, CA (US);

Sudhakar Dindukurti, Palo Alto, CA (US);

Anand Misra, Palo Alto, CA (US);

Arjun Sabnis, Palo Alto, CA (US);

Milad Sharif, Palo Alto, CA (US);

Ravinder Kumar, Palo Alto, CA (US);

Joshua Earle Polzin, Palo Alto, CA (US);

Arnav Goel, Palo Alto, CA (US);

Steven Dai, Palo Alto, CA (US);

Assignee:

SambaNova Systems, Inc., Palo Alto, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
G06F 13/28 (2013.01); G06F 2213/3808 (2013.01);
Abstract

A system is presented that includes two data processing systems that are coupled via a network, each data processing system including a reconfigurable processor with a reconfigurable processor memory, a host that is coupled to the reconfigurable processor and that includes a host processor and a host memory that is coupled to the host processor, and a network interface controller (NIC) that is operatively coupled to the reconfigurable processor and to the host processor. The reconfigurable processor of one of the data processing systems is configured to implement a virtual function that uses a virtual address for a memory access operation. An application programming interface (API) in the host processor translates the virtual address into a physical address, and the NIC uses the physical address to initiate a direct memory access operation at the reconfigurable processor memory or the host memory of the other data processing system.


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