The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 04, 2025

Filed:

Jul. 05, 2021
Applicant:

Proteantecs Ltd., Haifa, IL;

Inventors:

Evelyn Landman, Haifa, IL;

Eyal Fayneh, Givatayim, IL;

Shai Cohen, Haifa, IL;

Alex Khazin, Nesher, IL;

Assignee:

PROTEANTECS LTD., Haifa, IL;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3185 (2006.01); G01R 31/30 (2006.01); H03K 5/13 (2014.01);
U.S. Cl.
CPC ...
G01R 31/318594 (2013.01); G01R 31/3016 (2013.01); G01R 31/318536 (2013.01); H03K 5/13 (2013.01);
Abstract

Structural testing of a semiconductor integrated circuit (IC), including scanning test patterns or test conditions into internal circuits of the semiconductor IC, for example from a tester device. A timing margin may be measured during the structural test. The margin is measured based on a characteristic of a comparison between a test signal path of the semiconductor IC and a delayed signal path, the delayed signal path being a signal of the test signal path delayed by a variable delay time. An output of the margin measurement sensor may be scanned out, for instance to the tester device.


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