The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2025

Filed:

Sep. 05, 2023
Applicant:

Entropic Communications, Llc, New York, NY (US);

Inventors:

Madhukar Reddy, Carlsbad, CA (US);

Curtis Ling, Carlsbad, CA (US);

Tim Gallagher, Carlsbad, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04N 21/426 (2011.01); H04B 1/00 (2006.01); H04N 5/455 (2006.01); H04N 5/50 (2006.01); H04N 21/438 (2011.01); H04N 21/454 (2011.01); H04N 21/61 (2011.01);
U.S. Cl.
CPC ...
H04N 21/4263 (2013.01); H04B 1/0014 (2013.01); H04N 5/455 (2013.01); H04N 5/50 (2013.01); H04N 21/4382 (2013.01); H04N 21/4383 (2013.01); H04N 21/454 (2013.01); H04N 21/6143 (2013.01); H04N 21/6193 (2013.01);
Abstract

A wideband receiver system comprises a wideband analog-to-digital converter (ADC) module and a digital frontend (DFE) module. The wideband ADC is configured to concurrently digitize a band of frequencies comprising a plurality of desired channels and a plurality of undesired channels. The DFE module is coupled to the digital in-phase and quadrature signals. The DFE module is configured to select the plurality of desired channels from the digitized band of frequencies, and generate an intermediate frequency (IF) signal comprising the selected plurality of desired channels and having a bandwidth that is less than a bandwidth of the band of frequencies, where the generation comprises frequency shifting of the selected plurality of desired channels. The IF signal may be a digital signal and the DFE is configured to output the IF signal via a serial or parallel interface.


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