The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2025

Filed:

Sep. 20, 2021
Applicant:

Realtek Semiconductor Corp., Hsinchu, TW;

Inventors:

Meng-Che Li, Hsinchu, TW;

Bo-Kai Huang, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/033 (2006.01); G01R 31/3183 (2006.01);
U.S. Cl.
CPC ...
H04L 7/033 (2013.01); G01R 31/3183 (2013.01);
Abstract

A linearity test system for a chip, a linearity signal providing device, and a linearity test method for the chip are provided. The linearity test method for the chip includes steps as follows: providing a reference clock signal and a receiver input signal to a chip under test, wherein the reference clock signal and the receiver input signal have a phase difference in time domain; and determining a linearity of a phase interpolator of the chip under test based on a plurality of phase signals of the chip under test corresponding to the reference clock signal and the receiver input signal.


Find Patent Forward Citations

Li, Meng-Che. (2025). Linearity test system, linearity signal providing device, and linearity test method (U.S. Patent No. 12238196). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12238196

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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