The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2025

Filed:

May. 20, 2021
Applicants:

Hefei Xinsheng Optoelectronics Technology Co., Ltd., Anhui, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Qinghe Wang, Beijing, CN;

Tongshang Su, Beijing, CN;

Jun Wang, Beijing, CN;

Yongchao Huang, Beijing, CN;

Haitao Wang, Beijing, CN;

Ning Liu, Beijing, CN;

Jun Cheng, Beijing, CN;

Yingbin Hu, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); G11C 19/28 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78633 (2013.01); G11C 19/28 (2013.01); H01L 29/66742 (2013.01);
Abstract

A thin film transistor, including: at least one active layer pattern including a first conductive pattern, a second conductive pattern, and a semiconductor pattern; a gate on a side of the active layer pattern; a first electrode and a second electrode on a side of the gate away from the active layer pattern, and respectively electrically connected with the first conductive pattern and the second conductive pattern, a conductive shielding pattern is provided corresponding to the semiconductor pattern in at least one active layer pattern, the conductive shielding pattern is on a side of the semiconductor pattern away from the gate and is electrically connected with the first electrode, and a buffer layer is between the conductive shielding pattern and the semiconductor pattern; an orthographic projection of the conductive shielding pattern on a plane where the semiconductor pattern corresponding thereto is located at least partially covers the semiconductor pattern corresponding.


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