The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2025

Filed:

Jul. 30, 2021
Applicants:

Chengdu Boe Optoelectronics Technology Co., Ltd., Sichuan, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Huaping Sun, Beijing, CN;

Kai Zhang, Beijing, CN;

Erlong Song, Beijing, CN;

Qiang Fu, Beijing, CN;

Xingrui Cai, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/20 (2006.01); G09G 3/3225 (2016.01); G09G 3/3233 (2016.01); G09G 3/3258 (2016.01); H10K 59/131 (2023.01);
U.S. Cl.
CPC ...
G09G 3/2007 (2013.01); G09G 3/3225 (2013.01); G09G 3/3233 (2013.01); G09G 3/3258 (2013.01); H10K 59/131 (2023.02); G09G 2300/0408 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0852 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0254 (2013.01); G09G 2310/061 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/0247 (2013.01); G09G 2320/0252 (2013.01); G09G 2320/0257 (2013.01); G09G 2320/045 (2013.01); G09G 2320/0626 (2013.01);
Abstract

A pixel driving circuit includes a driving circuit, a first reset circuit, and a second reset circuit. The driving circuit is coupled to a first node and a second node, and is configured to output a driving current according to a voltage difference between the first node and the second node. The first reset circuit is coupled to the first node, a first initial signal terminal and a first reset signal terminal, and is configured to transmit a signal of the first initial signal terminal to the first node in response to a signal of the first reset signal terminal. The second reset circuit is coupled to the second node and a first power terminal, and is configured to transmit a signal of the first power supply terminal to the second node in response to a control signal.


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