The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2025

Filed:

May. 13, 2022
Applicant:

Novatek Microelectronics Corp., Hsinchu, TW;

Inventors:

Chien Te Tung, Taipei, TW;

Jen-Wei Liang, Taipei, TW;

Chih Feng Juan, New Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/04 (2023.01); G06F 7/499 (2006.01); G06F 15/78 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G06N 3/04 (2013.01); G06F 7/49942 (2013.01); G06F 15/7842 (2013.01); G11C 7/1012 (2013.01); G11C 7/1063 (2013.01); G11C 7/109 (2013.01);
Abstract

A compute-in-memory (CIM) macro device and an electronic device are proposed. The CIM macro device includes a CIM cell array including multiple CIM cells. First data is being divided into at least two bit groups including a first bit group which is the most significant bits of the first data and a second bit group which is the least significant bits of the first data, and the bit groups are respectively loaded in CIM cells of different columns of the CIM cell array. The electronic device includes at least one CIM macro and at least one processing circuit. The processing circuit is configured to receive and perform operation on parallel outputs respectively corresponding to the columns of the CIM cell array, where the parallel outputs include multiple correspondences, and where each of the correspondences includes most significant bits of an output activation and least significant bits of the output activation.


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