The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2025

Filed:

Jan. 19, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Changjun Park, Hwaseong-si, KR;

Jaesung Lee, Seongnam-si, KR;

Junghun Lim, Seongnam-si, KR;

Jungmin Oh, Incheon, KR;

Sangwon Bae, Suwon-si, KR;

Hyosan Lee, Seongnam-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C09K 13/10 (2006.01); C09K 13/08 (2006.01); H01L 21/306 (2006.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
C09K 13/10 (2013.01); C09K 13/08 (2013.01); H01L 21/30604 (2013.01); H10B 12/05 (2023.02); H10B 12/30 (2023.02);
Abstract

An etchant composition for etching a silicon germanium film includes, based on a total weight of the etchant composition, about 5 wt % to about 14 wt % of an oxidant, about 0.01 wt % to about 5 wt % of a fluorine compound, about 0.01 wt % to about 5 wt % of an amine compound, about 0.01 wt % to about 1 wt % of an alcohol compound having a hydrophilic head and a hydrophobic tail, about 60 wt % to about 90 wt % of an organic solvent, and a balance of water. A method of manufacturing an integrated circuit device includes: forming, on a substrate, a structure in which a plurality of silicon films and a plurality of silicon germanium films are alternately stacked; and selectively removing the plurality of silicon germanium films by using the etchant composition.


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