The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2025

Filed:

Jan. 11, 2021
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Helmut Brech, Lappersdorf, DE;

Albert Birner, Regensburg, DE;

John Twynam, Regensburg, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/78 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/417 (2006.01); H01L 29/778 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66462 (2013.01); H01L 21/02381 (2013.01); H01L 21/0254 (2013.01); H01L 21/7806 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/41758 (2013.01); H01L 29/7786 (2013.01);
Abstract

In an embodiment, a method for fabricating a semiconductor wafer includes: epitaxially growing a III-V semiconductor on a first surface of a foreign wafer having a thickness t, the first surface being capable of supporting the epitaxial growth of at least one III-V semiconductor layer, the wafer having a second surface opposing the first surface; removing portions of the III-V semiconductor to produce a plurality of mesas including the III-V semiconductor arranged on the first surface of the wafer; applying an insulation layer to regions of the wafer arranged between the mesas; and progressively removing portions of the second surface of the wafer, exposing the insulation layer in regions adjacent the mesas and producing a worked second surface.


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