The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2025

Filed:

May. 10, 2021
Applicant:

Fairchild Semiconductor Corporation, Phoenix, AZ (US);

Inventors:

Seungwon Im, Bucheon, KR;

Oseob Jeon, Seoul, KR;

JoonSeo Son, Seoul, KR;

Mankyo Jong, Bucheon, KR;

Olaf Zschieschang, Vaterstetten, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/051 (2006.01); H01L 23/31 (2006.01); H01L 23/373 (2006.01); H01L 23/538 (2006.01); H01L 25/07 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/565 (2013.01); H01L 23/3735 (2013.01); H01L 23/5385 (2013.01); H01L 24/00 (2013.01); H01L 25/072 (2013.01); H01L 23/051 (2013.01); H01L 23/3107 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/33 (2013.01); H01L 2224/291 (2013.01); H01L 2224/32227 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/33181 (2013.01); H01L 2224/83424 (2013.01); H01L 2224/83447 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06589 (2013.01);
Abstract

Implementations of semiconductor packages may include: a first substrate having a first dielectric layer coupled between a first metal layer and a second metal layer; a second substrate having a second dielectric layer coupled between a third metal layer and a fourth metal layer. A first die may be coupled with a first electrical spacer coupled in a space between and coupled with the first substrate and the second substrate and a second die may be coupled with a second electrical spacer coupled in a space between and coupled with the first substrate and the second substrate.


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