The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2025

Filed:

Jul. 03, 2023
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Paolo Di Febbo, Redwood City, CA (US);

Mohamed H. Abu-Rahma, Mountain View, CA (US);

Jelam K. Parekh, Milpitas, CA (US);

Yildiz Sinangil, Campbell, CA (US);

Mohammad Ghasemzadeh, San Jose, CA (US);

Anthony Ghannoum, Santa Clara, CA (US);

Chaminda N. Vidanagamachchi, San Jose, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); H03M 1/82 (2006.01);
U.S. Cl.
CPC ...
G11C 7/222 (2013.01); G11C 7/106 (2013.01); G11C 7/1087 (2013.01); H03M 1/82 (2013.01);
Abstract

An apparatus includes an in-memory compute circuit that includes a memory circuit configured to generate a set of products by combining received input values with respective weight values stored in rows of the memory circuit, and to combine the set of products to generate an accumulated output value. The in-memory compute circuit may further include a control circuit and a plurality of routing circuits, including a first routing circuit coupled to a first set of rows of the memory circuit. The control circuit may be configured to cause the first routing circuit to route groups of input values to different ones of the first set of rows over a plurality of clock cycles, and the memory circuit to generate, on a clock cycle following the plurality of clock cycles, a particular accumulated output value that is computed based on the routed groups of input values.


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