The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2025

Filed:

Sep. 13, 2022
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Keisuke Suda, Yokkaichi Mie, JP;

Ryota Suzuki, Yokkaichi Mie, JP;

Kenta Yamada, Yokkaichi Mie, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/06 (2006.01); G11C 5/02 (2006.01); G11C 16/04 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
G11C 16/0483 (2013.01); G11C 5/025 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/3436 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02);
Abstract

A semiconductor memory device includes memory blocks arranged in a first direction and bit lines that are arranged in a second direction, and are arranged with the memory blocks in a third direction. The memory block includes first conductive layers arranged in the third direction, a second conductive layer disposed on a side opposite to the bit lines in the third direction with respect to the first conductive layers, semiconductor layers that extend in the third direction, are opposed to the first conductive layers, have one ends in the third direction electrically connected to the second conductive layer, and have the other ends in the third direction electrically connected to the bit lines, and electric charge accumulating films disposed between the first conductive layers and the semiconductor layers. The first conductive layers and the second conductive layer are separated between the memory blocks.


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