The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2025

Filed:

Dec. 29, 2021
Applicant:

Realtek Semiconductor Corporation, Hsinchu, TW;

Inventor:

I-Hao Chiang, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 15/00 (2006.01); G11C 11/408 (2006.01); G11C 11/417 (2006.01); G11C 11/419 (2006.01); G11C 15/04 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
G11C 15/04 (2013.01); G11C 11/4085 (2013.01); G11C 11/417 (2013.01); G11C 11/419 (2013.01); H03K 19/20 (2013.01);
Abstract

A masking circuit of a content addressable memory (CAM) includes a masking control circuit and a level control circuit. The masking control circuit generates a masking signal according to a word line (WL) signal and a write enablement (WE) signal. When both the WL and WE signals are at a first level, the masking signal is a first masking signal; when they are at different levels respectively, the masking signal is a second masking signal. The level control circuit generates a level control signal according to the masking signal for determining whether to pull a voltage level of a match line of the CAM to a predetermined level. When the masking signal is the first masking signal, the level control circuit pulls the voltage level to the predetermined level; and when the masking signal is the second masking signal, the level control circuit does not interfere in the voltage level.


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