The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 18, 2025

Filed:

Oct. 13, 2023
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

Do Young Jung, Paju-si, KR;

Byeong Seong So, Paju-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3233 (2016.01); G09G 3/3258 (2016.01); G09G 3/3266 (2016.01); G09G 3/3291 (2016.01);
U.S. Cl.
CPC ...
G09G 3/3233 (2013.01); G09G 3/3258 (2013.01); G09G 3/3266 (2013.01); G09G 3/3291 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0243 (2013.01);
Abstract

A pixel circuit according to an embodiment and a display device including the same are disclosed. The pixel circuit includes a driving element including a driving element including a first electrode connected to a pixel driving voltage line, a gate electrode connected to a first node, and a second electrode connected to a second node, a first switch element configured to supply a data voltage to the first node in response to a first gate signal, a second switch element configured to supply an initialization voltage to the first node in response to a second gate signal, a third switch element configured to supply a reference voltage to a third node in response to a third gate signal, a fourth switch element configured to connect the second node and the third node in response to a fourth gate signal, a first capacitor connected between the first node and the second node, a second capacitor connected between the pixel driving voltage line and the second node, a third capacitor connected between a gate electrode of the second switch element and the second node and a light-emitting element connected between the third node and a low-potential power voltage line.


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